commit 4e37805952e638925433dc0657f9720792f0d43f
Author: Carl Michal <michal@phas.ubc.ca>
Date:   Fri Jun 15 21:59:14 2018 -0700

    CM changes for Xnmr - sync and trigger stamp capture - for rx_path_top.vhd only.

diff --git a/src/rx_path_top/rx_path/synth/rx_path_top.vhd b/src/rx_path_top/rx_path/synth/rx_path_top.vhd
index 9384e92..eeaa24c 100644
--- a/src/rx_path_top/rx_path/synth/rx_path_top.vhd
+++ b/src/rx_path_top/rx_path/synth/rx_path_top.vhd
@@ -18,7 +18,8 @@ entity rx_path_top is
       iq_width             : integer := 12;
       invert_input_clocks  : string := "OFF";
       smpl_buff_rdusedw_w  : integer := 11; --bus width in bits 
-      pct_buff_wrusedw_w   : integer := 12  --bus width in bits 
+      pct_buff_wrusedw_w   : integer := 12;  --bus width in bits 
+      trig_pulse_duration  : integer := 10000 -- duration of trig pulse output
       );
    port (
       clk                  : in std_logic;
@@ -45,7 +46,7 @@ entity rx_path_top is
       clr_smpl_nr          : in std_logic;
       ld_smpl_nr           : in std_logic;
       smpl_nr_in           : in std_logic_vector(63 downto 0);
-      smpl_nr_cnt          : out std_logic_vector(63 downto 0);
+      smpl_nr_cnt          : buffer std_logic_vector(63 downto 0);
       --flag control
       tx_pct_loss          : in std_logic;
       tx_pct_loss_clr      : in std_logic;
@@ -53,7 +54,13 @@ entity rx_path_top is
       smpl_cmp_start       : in std_logic;
       smpl_cmp_length      : in std_logic_vector(15 downto 0);
       smpl_cmp_done        : out std_logic;
-      smpl_cmp_err         : out std_logic
+      smpl_cmp_err         : out std_logic;
+		
+		--CM
+		ext_flag					: in std_logic; -- triggers capture of current sample number
+		trig_out_pulse			: out std_logic; -- on next div_clk, hold this high for trig_pulse_duration samples.
+		div_clk					: out std_logic; -- sample clock divided by 16
+		trig_sync            : in std_logic   -- tells us to provide the trig_out_pulse
      
         );
 end rx_path_top;
@@ -84,7 +91,17 @@ signal smpl_nr_in_sync        : std_logic_vector(63 downto 0);
 signal smpl_cmp_start_sync    : std_logic;
 signal smpl_cmp_length_sync   : std_logic_vector(15 downto 0);
 
-
+--CM: 
+signal ext_flag_sync          : std_logic;
+signal ext_flag_sync_d        : std_logic;
+signal since_wrreq            : std_logic_vector(1 downto 0);
+signal flag_capture_q         : std_logic_vector(63 downto 0);
+signal trigger_seen				: std_logic;
+signal last_trigger				: std_logic;
+signal trig_sync_sync	      : std_logic;
+signal trigger_time				: std_logic_vector(63 downto 0);
+signal last_bit3					: std_logic;
+signal my_mode                : std_logic_vector(1 downto 0);
 
 --inst0 
 signal inst0_fifo_wrreq       : std_logic;
@@ -150,6 +167,13 @@ port map(clk, '1', test_ptrn_en, test_ptrn_en_sync);
 sync_reg11 : entity work.sync_reg 
 port map(clk, '1', smpl_cmp_start, smpl_cmp_start_sync);
 
+--CM my reg:
+sync_reg12 : entity work.sync_reg
+port map(clk, '1', ext_flag, ext_flag_sync);
+
+sync_reg13 : entity work.sync_reg
+port map(clk, '1', trig_sync, trig_sync_sync);
+
 
 bus_sync_reg0 : entity work.bus_sync_reg
 generic map (2)
@@ -327,22 +351,109 @@ delay_registers : process(clk, reset_n)
 begin
    if reset_n = '0' then 
       delay_chain <= (others=>(others=>'0'));
+		last_trigger <= '0';
+		trigger_seen <= '0';
+		trig_out_pulse <= '0';
    elsif (clk'event AND clk='1') then 
       for i in 0 to 5 loop
          if i=0 then 
-            delay_chain(i) <= inst3_q;
+			if (ext_flag_sync_d = '0') then 
+					delay_chain(i) <= inst3_q;
+				else
+					delay_chain(i) <= flag_capture_q;
+				end if;
          else 
             delay_chain(i) <= delay_chain(i-1);
          end if;
       end loop;
+		if inst0_fifo_wrreq = '1' then
+		   since_wrreq <= (others=>'0');
+		else --add one to since_wrreq:
+		  since_wrreq(1) <= since_wrreq(1) xor since_wrreq(0);
+		  since_wrreq(0) <= not since_wrreq(0);
+		end if;
+		if ext_flag_sync = '0' then
+--          if ( mimo_en_sync = '0' and ddr_en_sync = '1' and since_wrreq(0) = '1') then -- siso ddr last half
+--             flag_capture_q <= '1' & smpl_nr_cnt(62 downto 1) & '1';
+--			elsif (mimo_en_sync = '0' and ddr_en_sync = '0' and since_wrreq(1) ='1' ) then -- siso sdr last half
+--			    flag_capture_q <= '1' & smpl_nr_cnt(62 downto 1) & '1';
+--			elsif ((mimo_en_sync = '1' or trxiqpulse = '1') and (ch_en_sync(0) = '0' or ch_en_sync(1) ='0') and since_wrreq(1) = '1') then -- mimo, single channel last half.
+--             flag_capture_q <= '1' & smpl_nr_cnt(62 downto 1) & '1';
+--			else     -- mimo ddr and first half of all the others.
+
+--         if (since_wrreq(1) = '1') then
+--             flag_capture_q <= '1' & smpl_nr_cnt(62 downto 1) & '1';
+--		else
+         if my_mode ="00" and since_wrreq(0) = '1'  then
+			   flag_capture_q <= '1' & smpl_nr_cnt(62 downto 1 ) & '1';
+			elsif my_mode(1) = '1' and since_wrreq(1) = '1'  then
+			  flag_capture_q <= '1' & smpl_nr_cnt(62 downto 1 ) & '1';
+			else
+             flag_capture_q <= '1' & smpl_nr_cnt(62 downto 0);
+		   end if;
+		end if;
+		if (trigger_seen = '1' AND last_bit3 = '0' AND smpl_nr_cnt(3) = '1') then
+			trigger_time <= smpl_nr_cnt;
+			trig_out_pulse <= '1';
+			trigger_seen <= '0';
+		elsif (smpl_nr_cnt > std_logic_vector(unsigned(trigger_time ) + to_unsigned(trig_pulse_duration,64))) then
+		  trig_out_pulse <= '0';
+	   end if;
+   	last_bit3 <= smpl_nr_cnt(3);
+		if (trig_sync_sync = '1' AND last_trigger = '0') then
+		   trigger_seen <= '1';			
+		end if;
+		last_trigger <= trig_sync_sync;
+		ext_flag_sync_d <= ext_flag_sync;
    end if;
 end process;
         
  inst2_pct_hdr_1 <=  delay_chain(5);      
-  
+ div_clk <= smpl_nr_cnt(3);
+
+ my_mode <= "00" when (mimo_en_sync = '0' and ddr_en_sync = '1') else
+           "01" when ((mimo_en_sync = '1' or trxiqpulse_sync = '1') and ch_en_sync = "11") else
+           "10" when ((mimo_en_sync = '1' or trxiqpulse_sync = '1') and (ch_en_sync(0) xor ch_en_sync(1)) = '1' ) else
+			  "11";
+
 end arch;   
 
+-- '00' is SISO DDR - here there is one clock tick per sample, but the counter increments every second time
+-- '01' is mimo ddr or txiq 2 channel. Here, the counter takes care of itself.
+-- '10' is mimo ddr single channel. The rfic transmits both channels, but we ignore half. So there are 2 clocks per sample, 4 clocks per counter increment
+-- '11' SISO SDR - again two clocks per sample, four per increment.
+-- so 10 and 11 are treated the same,
 
+-- So, based on the table below and the int_mode logic below that, which appear to not be completely
+-- consistent with each other, I believe:
+-- (mimo_en=0 and ddr_en=1) -> SISO DDR
+-- (mimo_en = 1 or trxiqpulse=1) and ch_en = '11 -> mimo ddr (or TXIQ, but same deal for me).
+-- (mimo_en = 1 or trxiqpulse =1 ) and (ch_en(0) xor ch_en(1)) -> single channel mimo ddr.
+-- otherwise is SISO SDR (single data rate).
 
+-- I think it all means that the ddr flag only has meaning if trxiqpulse=0. trxiq implies ddr.
 
+--copied from txiq.vhd (CM)
+-- ----------------------------------------------------------------------------
+--Truth table for mode selection
+-- ----------------------------------------------------------------------------
+-- Mode       | TRXIQ_PULSE  | MIMO DDR  | MIMO DDR  | MIMO DDR  |SISO SDR   | SISO DDR  |
+--            |              |  all ch.  |  1 ch.    |  2 ch.    |           |           |
+-- trxiqpulse |       H      |     L     |    L      |    L      |     L     |     L     |
+-- ddr_en     |       X      |     H     |    H      |    H      |     H     |     L     |
+-- mimo_en    |       X      |     H     |    H      |    H      |     L     |     L     |
+-- ch_en      |       XX     |     HH    |   LH      |    HL     |     XX    |     XX    |
+
+-----------------------------------------------------------------------------
+--Internal mode selection for DIQ position
+-- "00" - MIMO DDR both channels enabled, SISO DDR, TXIQ_PULSE
+-- "01" - MIMO DDR, TXIQ_PULSE first channel enabled
+-- "10" - MIMO DDR, TXIQ_PULSE second channel enabled
+-- "11" - SISO SDR 
+-- ----------------------------------------------------------------------------
+ --int_mode <= "00" when (mimo_en='0' AND ddr_en='1') OR ((mimo_en='1' OR trxiqpulse ='1') AND ch_en="11") else 
+--             "01" when ((mimo_en='1' OR trxiqpulse ='1') AND ch_en="01") else
+--             "10" when ((mimo_en='1' OR trxiqpulse ='1') AND ch_en="10") else
+--             "11";
+             
 
